The present invention is directed to the sending and receiving of data packets in a control system employing intelligent DMA controllers having the capability of using buffer chains established by a host processor, and more particular to buffer management by DMA controllers to achieve efficient use of a buffer memory area for receiving data packets of an unknown size.
In control systems external data is received by a receiving device such as a media access interface chip, which in the following may be called a System Media Access Controller (SMAC), this data is passed to a DMA controller which, acting in cooperation with a host processor, stores the received data in a system memory thereby providing the host processor with access for processing this data.
Commercially available off-the-shelf intelligent DMA controllers are constructed with a capability which allows use of buffer chains established by the host processor to send or receive data packets. Prior to operation of the control system the host processor configures a portion of the system memory into a plurality of data buffers which are assigned to receive the received data. The data buffers are sized large enough to accommodate the largest packet of received data that is expected. Since the arriving packets are of an unknown size, in order to ensure proper operation of the control system each buffer must be large enough to receive a maximum sized data packet or a system error will occur. It is also known, however, that the maximum sized data packet will be much larger than the average or typical sized data packet. Further, it is common in control systems that bursts of numerous small data packets will frequently occur resulting in a large number of data packets being stored in data buffers capable of holding significantly more data.
In existing control systems a single memory area is divided into the substantially equal sized data buffers, each of which corresponds to one of a number of buffer descriptors. The buffer descriptors are combined by the host processor to form buffer chains whereby irrespective of the amount of data, data packets are sequentially entered in the equally sized data buffers. A configuration of this type results in inefficient use of the single memory area when data packets smaller than a maximum data packet is received. This inefficient fragmentation requires a larger than necessary memory area to be designed for the data buffering in a control system, raising the overall cost of the control system. An alternative to adding additional memory is to limit the number of data buffers available, however, this solution increases the potential of reducing the performance of the control system by forcing system functions to wait for buffer availability.
Therefore, it has been deemed desirable to develop a DMA controller for use in a control system which makes it possible to provide dynamic fracturing or fragmentation of a single memory buffer area into smaller memory fragments, as well as including the capability of recombining the used memory fragments for future use.